Modeling Substrate Coupling Eeects Using a Layout-to-circuit Extraction Program

using a Layout-to-Circuit Extraction Program Arjan van Genderen, Nick van der Meijs Delft University of Technology Faculty of Information Technology and Systems ITS Circuits and Systems Group Mekelweg 4, 2628 CD Delft, the Netherlands tel. +31 (0)15 278 6258 fax. +31 (0)15 278 6190 farjan,[email protected] Abstract| Substrate coupling e ects in integrated circuits can severely degenerate the performance of these circuits. Their impact can be veri ed by computing the substrate resistances between the parts of the circuit that inject noise into the substrate and those parts that are sensitive to it. We will describe two di erent methods for substrate resistance calculation and how they have been implemented in a practical layout-to-circuit extraction program called SPACE. One method is an accurate 3D boundary-element technique that can be used for circuits containing up to few hundreds of substrate terminals. The other method is a fast interpolation technique that can be used for complete VLSI circuits. We will show how the user can specify the substrate coupling e ects that need to be modeled and we will give some examples.